fsycl-link

Tells the compiler to perform a partial link of device binaries to be used with Field Programmable Gate Array (FPGA). This content is specific to DPC++.

Syntax

Linux:

-fsycl-link[=value]

Windows:

-fsycl-link[=value]

Arguments

value

Can be one of the following:

early

Tells the compiler to generate an HTML report when the partial link is created. This capability lets you check the program if need be.

You can resume from this point and generate an FPGA image by specifying option -fintelfpga with the generated binary.

image

Tells the compiler to generate an FPGA bitstream. It will then be ready to be linked and used on an FPGA board.

image takes much longer to generate than does early.

Default

OFF	No partial link of device binaries is performed.

Description

This option tells the compiler to perform a partial link of device binaries to be used with FPGA.

This partial link is then wrapped by the offload wrapper, allowing the device binaries to be linked by the host compiler or linker.

If you do not specify a value, the following occurs:

When used with just -fsycl (-fsycl -fsycl-link), the driver will generate a host linkable device object.
When also used with -fintelfpga (-fsycl -fintelfpga -fsycl-link), the behavior is the same as specifying -fsycl-link=early.

IDE Equivalent

Visual Studio: Linker > General > Generate partially linked device object to be used with the host link

Eclipse: Linker > General > Generate partially linked device object to be used with the host link

Alternate Options

None