Rijndael128GCMInitManaged

Syntax

IppStatus ippsRijndael128GCMInitManaged(IppAESGCMbehaviour flag, const Ipp8u* pKey, IppsRijndaelKeyLength keyLen, IppsRijndael128GCMState* pState);

Parameters

flag	A flag that defines characteristics for the AES-GCM implementation.
pKey	Pointer to the secret key.
keyLen	Length of the secret key.
pState	Pointer to the IppsRijndael128GCMState context.

Description

This function is declared in the ippcp.h file. The function takes characteristics of the AES-GCM implementation from the input parameter flag and initializes the memory pointed by pState as the IppsRijndael128GCMState context needed to perform encryption and/or decryption that uses the specified AES-GCM implementation. In addition, the function uses the initialization variable and additional authenticated data to provide all necessary key material for both encryption and decryption. The flag parameter is the following enumerator:

typedef enum {
    ippAESGCMdefault,
    ippAESGCMsafe,
    ippAESGCMtable2K
}
IppAESGCMbehaviour;

where the values define the following requirements for the characteristics of the AES-GCM implementation:

ippAESGCMdefault	Minimum memory, that is, the minimum size of the context
ippAESGCMsafe	Maximum protection against timing attacks
ippAESGCMtable2K	Maximum performance of the implementation

Call Rijndael128GCMInitManaged with the same value of flag as used in the previous call to Rijndael128GCMGetSizeManaged.

Note

If your system is based on microprocessors that support an AES instruction set, the AES-GCM implementation will meet all the above requirements regardless of the value of flag.

Optimization Notice
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804

Optimization Notice

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804

Return Values