Shift Intrinsics

The Intel® Streaming SIMD Extensions 2 (Intel® SSE2) intrinsics for integer shift operations are listed in this topic. The prototypes for the Intel® SSE2 intrinsics are in the emmintrin.h header file.

The results of each intrinsic operation are placed in registers. The information about what is placed in each register appears in the tables below, in the detailed explanation of each intrinsic. R, R0, R1...R7 represent the registers in which results are placed.

Note

The count argument is one shift count that applies to all elements of the operand being shifted. It is not a vector shift count that shifts each element by a different amount.

Intrinsic	Operation	Shift Type	Corresponding Intel® SSE2 Instruction
_mm_slli_si128	Shift left	Logical	PSLLDQ
_mm_slli_epi16	Shift left	Logical	PSLLW
_mm_sll_epi16	Shift left	Logical	PSLLW
_mm_slli_epi32	Shift left	Logical	PSLLD
_mm_sll_epi32	Shift left	Logical	PSLLD
_mm_slli_epi64	Shift left	Logical	PSLLQ
_mm_sll_epi64	Shift left	Logical	PSLLQ
_mm_srai_epi16	Shift right	Arithmetic	PSRAW
_mm_sra_epi16	Shift right	Arithmetic	PSRAW
_mm_srai_epi32	Shift right	Arithmetic	PSRAD
_mm_sra_epi32	Shift right	Arithmetic	PSRAD
_mm_srli_si128	Shift right	Logical	PSRLDQ
_mm_srli_epi16	Shift right	Logical	PSRLW
_mm_srl_epi16	Shift right	Logical	PSRLW
_mm_srli_epi32	Shift right	Logical	PSRLD
_mm_srl_epi32	Shift right	Logical	PSRLD
_mm_srli_epi64	Shift right	Logical	PSRLQ
_mm_srl_epi64	Shift right	Logical	PSRLQ

__m128i _mm_slli_si128(__m128i a, int imm)

Shifts the 128-bit value in a left by imm bytes while shifting in zeros. imm must be an immediate.

R
a << (imm * 8)

__m128i _mm_slli_epi16(__m128i a, int count)

Shifts the 8 signed or unsigned 16-bit integers in a left by count bits while shifting in zeros.

R0	R1	...	R7
a0 << count	a1 << count	...	a7 << count

__m128i _mm_sll_epi16(__m128i a, __m128i count)

Shifts the 8 signed or unsigned 16-bit integers in a left by count bits while shifting in zeros.

R0	R1	...	R7
a0 << count	a1 << count	...	a7 << count

__m128i _mm_slli_epi32(__m128i a, int count)

Shifts the 4 signed or unsigned 32-bit integers in a left by count bits while shifting in zeros.

R0	R1	R2	R3
a0 << count	a1 << count	a2 << count	a3 << count

__m128i _mm_sll_epi32(__m128i a, __m128i count)

Shifts the 4 signed or unsigned 32-bit integers in a left by count bits while shifting in zeros.

R0	R1	R2	R3
a0 << count	a1 << count	a2 << count	a3 << count

__m128i _mm_slli_epi64(__m128i a, int count)

Shifts the 2 signed or unsigned 64-bit integers in a left by count bits while shifting in zeros.

R0	R1
a0 << count	a1 << count

__m128i _mm_sll_epi64(__m128i a, __m128i count)

Shifts the 2 signed or unsigned 64-bit integers in a left by count bits while shifting in zeros.

R0	R1
a0 << count	a1 << count

__m128i _mm_srai_epi16(__m128i a, int count)

Shifts the 8 signed 16-bit integers in a right by count bits while shifting in the sign bit.

R0	R1	...	R7
a0 >> count	a1 >> count	...	a7 >> count

__m128i _mm_sra_epi16(__m128i a, __m128i count)

Shifts the 8 signed 16-bit integers in a right by count bits while shifting in the sign bit.

R0	R1	...	R7
a0 >> count	a1 >> count	...	a7 >> count

__m128i _mm_srai_epi32(__m128i a, int count)

Shifts the 4 signed 32-bit integers in a right by count bits while shifting in the sign bit.

R0	R1	R2	R3
a0 >> count	a1 >> count	a2 >> count	a3 >> count

__m128i _mm_sra_epi32(__m128i a, __m128i count)

Shifts the 4 signed 32-bit integers in a right by count bits while shifting in the sign bit.

R0	R1	R2	R3
a0 >> count	a1 >> count	a2 >> count	a3 >> count

__m128i _mm_srli_si128(__m128i a, int imm)

Shifts the 128-bit value in a right by imm bytes while shifting in zeros. imm must be an immediate.

R
srl(a, imm*8)

__m128i _mm_srli_epi16(__m128i a, int count)

Shifts the 8 signed or unsigned 16-bit integers in a right by count bits while shifting in zeros.

R0	R1	...	R7
srl(a0, count)	srl(a1, count)	...	srl(a7, count)

__m128i _mm_srl_epi16(__m128i a, __m128i count)

Shifts the 8 signed or unsigned 16-bit integers in a right by count bits while shifting in zeros.

R0	R1	...	R7
srl(a0, count)	srl(a1, count)	...	srl(a7, count)

__m128i _mm_srli_epi32(__m128i a, int count)

Shifts the 4 signed or unsigned 32-bit integers in a right by count bits while shifting in zeros.

R0	R1	R2	R3
srl(a0, count)	srl(a1, count)	srl(a2, count)	srl(a3, count)

__m128i _mm_srl_epi32(__m128i a, __m128i count)

Shifts the 4 signed or unsigned 32-bit integers in a right by count bits while shifting in zeros.

R0	R1	R2	R3
srl(a0, count)	srl(a1, count)	srl(a2, count)	srl(a3, count)

__m128i _mm_srli_epi64(__m128i a, int count)

Shifts the 2 signed or unsigned 64-bit integers in a right by count bits while shifting in zeros.

R0	R1
srl(a0, count)	srl(a1, count)

__m128i _mm_srl_epi64(__m128i a, __m128i count)

Shifts the 2 signed or unsigned 64-bit integers in a right by count bits while shifting in zeros.

R0	R1
srl(a0, count)	srl(a1, count)