Performs a packed bit test of two float64 256-bit or 128-bit vectors to set the ZF flag. The corresponding Intel® AVX instruction is VTESTPD.
Syntax
extern __m256 _mm256_testz_pd(__m256 s1, __m256 s2); |
extern __m128 _mm_testz_pd(__m128 s1, __m128 s2); |
Arguments
s1 |
first float64 source vector |
s2 |
second float64 source vector |
Description
Allows setting of the ZF flag. The ZF flag is set based on the result of a bitwise AND operation between the first and second source vectors. The corresponding instruction, VTESTPD, sets the ZF flag if all the resulting bits are 0. If the resulting bits are non-zeros, the instruction clears the ZF flag.
The _mm_testz_pd intrinsic sets the ZF flag according to results of the 128-bit float64 source vectors. The _m256_testz_pd intrinsic sets the ZF flag according to the results of the 256-bit float64 source vectors.
Note
Intel® AVX instructions include a full compliment of 128-bit SIMD instructions. Such Intel® AVX instructions, with vector length of 128-bits, zeroes the upper 128 bits of the YMM register. The lower 128 bits of the YMM register is aliased to the corresponding SIMD XMM register.
Returns
Non-zero if ZF flag is set
Zero if the ZF flag is not set