This topic lists the options that provide new functionality in this release.
Some compiler options are only available on certain systems, as indicated by these labels:
Label |
Meaning |
|---|---|
i32 |
The option is available on systems using IA-32 architecture. |
i64em |
The option is available on systems using Intel® 64 architecture. |
If no label appears, the option is available on all supported systems.
If "only" appears in the label, the option is only available on the identified system.
For more details on the options, refer to the individual option descriptions.
For information on conventions used in this table, see Conventions.
New compiler options are listed in tables below:
The first table lists new options that are available on Windows* systems.
The second table lists new options that are available on Linux* and Mac OS* X systems. If an option is only available on one of these operating systems, it is labeled.
Windows* OS Options |
Description |
Default |
|---|---|---|
/arch:CORE-AVX-I |
May generate Intel® Advanced Vector Extensions (Intel® AVX), including instructions in Intel® Core 2™ processors in process technology smaller than 32nm, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions. |
OFF |
/arch:CORE-AVX2 |
May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. |
OFF |
/openmp |
This is an alternate name for option /Qopenmp. |
OFF |
/QaxCORE-AVX-I |
May generate Intel® Advanced Vector Extensions (Intel® AVX), including instructions in Intel® Core 2™ processors in process technology smaller than 32nm, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions. |
OFF |
/QaxCORE-AVX2 |
May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. |
OFF |
/Qfma[-] |
Determines whether the compiler generates fused multiply-add (FMA) instructions if such instructions exist on the target processor. |
/Qfma |
/Qopt-mem-layout-trans[:n] |
Controls the level of memory layout transformations performed by the compiler. |
/Qopt-mem-layout-trans:2 |
/Qvla[-] |
Determines whether variable length arrays are enabled. |
/Qvla- |
/QxCORE-AVX-I |
May generate Intel® Advanced Vector Extensions (Intel® AVX), including instructions in Intel® Core 2™ processors in process technology smaller than 32nm, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions. Optimizes for a future Intel processor. |
OFF |
/QxCORE-AVX2 |
May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for a future Intel processor. |
OFF |
/QxSSSE3_ATOM |
This option replaces option /QxSSE3_ATOM, which is deprecated in this release. |
OFF |
Linux* OS and Mac OS* X Options |
Description |
Default |
|---|---|---|
-axCORE-AVX-I |
May generate Intel® Advanced Vector Extensions (Intel® AVX), including instructions in Intel® Core 2™ processors in process technology smaller than 32nm, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions. |
OFF |
-axCORE-AVX2 |
May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. |
OFF |
-f[no-]asynchronous-unwind-tables |
Determines whether unwind information is precise at an instruction boundary or at a call boundary. |
-fasynchronous-unwind-tables |
-f[no-]blocks |
Determines whether Apple* blocks are enabled or disabled. |
-fblocks |
-[no-]fma |
Determines whether the compiler generates fused multiply-add (FMA) instructions if such instructions exist on the target processor. |
-fma |
-f[no-]merge-debug-strings |
Causes the compiler to pool strings used in debugging information. |
-fno-merge-debug-strings |
-f[no-]ms-dialect[=ver] |
Enables support for a language dialect that is compatible with Microsoft* Windows, while maintaining link compatibility with gcc. This option was previously restricted to Mac OS* X, but it is now also available in Linux* OS. |
-fno-ms-dialect |
-fopenmp |
This is an alternate name for option -openmp. |
OFF |
-gdwarf-3 |
Enables generation of debugging information using the DWARF Version 3 format. |
OFF |
-march=core-avx-i |
May generate Intel® Advanced Vector Extensions (Intel® AVX), including instructions in Intel® Core 2™ processors in process technology smaller than 32nm, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions. |
OFF |
-march=core-avx2 |
May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. |
OFF |
-march=corei7-avx |
Generates code for processors that support Intel(R) Advanced Vector Extensions (Intel® AVX), Intel® SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions. |
OFF |
-march=corei7 |
Generates code for Intel® Core™ i7 processors that support Intel(R) SSE4 Efficient Accelerated String and Text Processing instructions. May also generate Intel® SSE4 Vectorizing Compiler and Media Accelerator, Intel® SSSE3, SSE3, SSE2, and SSE instructions and it may optimize for the Intel® Core™ processor family. |
OFF |
-march=atom |
Generates code for processors that support MOVBE instructions, depending on the setting of option -minstruction (Linux* OS and Mac OS* X) or /Qinstruction (Windows* OS). May also generate Intel® SSSE3, SSE3, SSE2, and SSE instructions for Intel processors. Optimizes for the Intel® Atom™ processor and Intel® Centrino® Atom™ Processor Technology. |
OFF |
-march=pentium-m |
Generates code for Intel® Pentium® M processors. |
OFF |
-masm=dialect |
Tells the compiler to generate the assembler output file using a selected dialect. |
-masm=att |
-opt-mem-layout-trans[=n] |
Controls the level of memory layout transformations performed by the compiler. |
-opt-mem-layout-trans=2 |
-xCORE-AVX-I |
May generate Intel® Advanced Vector Extensions (Intel® AVX), including instructions in Intel® Core 2™ processors in process technology smaller than 32nm, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions. Optimizes for a future Intel processor. |
OFF |
-xCORE-AVX2 |
May generate Intel® Advanced Vector Extensions 2 (Intel® AVX2), Intel® AVX, SSE4.2, SSE4.1, SSSE3, SSE3, SSE2, and SSE instructions for Intel® processors. Optimizes for a future Intel processor. |
OFF |
-xSSSE3_ATOM |
This option replaces option -xSSE3_ATOM, which is deprecated in this release. |
OFF |
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